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AD8303 Scheda tecnica(PDF) 10 Page - Analog Devices |
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AD8303 Scheda tecnica(HTML) 10 Page - Analog Devices |
10 / 16 page AD8303 REV. 0 –10– DAC REGISTER A DAC A DAC B AD8303 VOUTA VOUTB CS SDI LDA LDB MSB RS SHDN 12 MSB RESET LOAD 12 12-BIT SHIFT REGISTER 12 CLK D Q11–Q0 en CLK DAC REGISTER B MSB RESET LOAD Figure 27. AD8303 Digital Section Functional Block Diagram Separate Load pins (LDA and LDB) are provided to control the flow of data from the shift register to the DAC registers. After the new value is loaded in the serial-input register, it can be asynchronously transferred to either DAC register by strobing the appropriate Load pin (LDA or LDB). The Load pins are level sensitive, so they should be returned high before any new data is loaded into the serial-input register. RESET (RS) AND MSB PINS The RS pin forces both of the DAC registers to a known state, based on the logic level on the MSB pin. If MSB is a logic zero, then forcing RS low will set the DAC latches to all zeros and the DAC output voltage will be zero volts. If MSB is a logic one, then RS will force the DAC latches to one-half scale (800H) and the DAC outputs will be 1.024 V. The half-scale reset is useful for systems where the DAC output is referenced to a “false ground” (see the Generating Bipolar Outputs with a Single Supply section of this data sheet for more information). The reset function is useful for setting the DAC outputs to zero at power-up or after a power supply interruption. Test systems and motor controllers are two of many applications which benefit from powering up to a known state. The reset pulse can be generated by the microprocessor’s power-on RESET signal, by an output from the microprocessor (Figure 33), or by an external resistor and capacitor (Figure 34). RS and MSB have level-sensitive thresholds. The RS input overrides other logic inputs (specifically, LDA and LDB). However, LDA and LDB should be set high before RS goes high. If LDA or LDB are kept low, then the contents of the shift register will be transferred to the DAC register as soon as RS goes high. DIGITAL INTERFACE The AD8303 has a double-buffered serial data input. The serial-input register is separate from the two DAC registers, which allows preloading of a new data value into the serial register without disturbing the present DAC values. A functional block diagram of the digital section is shown in Figure 27, while Table I contains the truth table for the control logic inputs. Three pins control the serial data input. Data at the Serial Data Input (SDI) is clocked into the shift register on the rising edge of CLK. Data is entered in MSB-first format. Twelve clock pulses are required to load the 12-bit DAC value. If additional bits are clocked into the shift register, for example when a µC sends two 8-bit bytes, the MSBs are ignored (Figure 28). The CLK pin is only enabled when Chip Select (CS) is low. If only one AD8303 is connected to a serial data bus, then CS can be tied (hardwired) to ground. BYTE 1 BYTE 2 MSB LSB MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11–D0: 12-BIT DAC VALUE X = DON'T CARE THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC Figure 28. Typical AD8303-Microprocessor Serial Data Input Format |
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