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AD6645ASVZ-105 Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD6645ASVZ-105 Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 24 page AD6645 Rev. D | Page 6 of 24 Test AD6645ASQ-80/ AD6645ASV-80 AD6645ASQ-105/ AD6645ASV-105 Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit DATA-READY (DRY4)/DATA(D13:0),, OVR Data-Ready to DATA Delay (Hold Time) tH_DR Full V Note 55 Note 55 50% Duty Cycle Full V 6.6 7.2 7.9 5.1 5.7 6.4 ns Data-Ready to DATA Delay (Setup Time) tS_DR Full V Note 55 Note 55 50% Duty Cycle Full V 2.1 3.6 5.1 0.6 2.1 3.5 ns APERTURE DELAY tA 25°C V −500 −500 ps APERTURE UNCERTAINTY (JITTER) tJ 25°C V 0.1 0.1 ps rms 1 Several timing parameters are a function of tENC and tENCH. 2 Several timing parameters are a function of tENCL and tENCH. 3 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E. 4 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 5 Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle. tS_DR tA AIN N N + 1 N + 2 N + 3 N + 4 tENC tENCH tENCL tE_FL tE_RL tE_DR tS_E tH_E tDR tH_DR N N – 1 N – 3 D[13:0], OVR DRY N + 4 N + 3 N + 2 N + 1 N ENCODE, ENCODE N – 2 Figure 2. Timing Diagram |
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