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74LVC821APW Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74LVC821APW Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 20 page 74LVC821A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 23 November 2012 10 of 20 NXP Semiconductors 74LVC821A 10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state 11. Waveforms Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency mna894 CP input Qn output tPHL tPLH tW 1/fmax VM VOH VI GND VOL VM Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. Data set-up and hold times for the Dn input to the CP input mna202 GND GND th th tsu tsu VM VM VM VI VOH VOL VI Qn output CP input Dn input |
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