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AD7804BN Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD7804BN Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 28 page AD7804/AD7805/AD7808/AD7809 REV. A –4– (VDD = 3.3 V 10% to 5 V 10%; AGND = DGND = 0 V; Reference = Internal Reference. All specifications TMIN to TMAX unless otherwise noted.) Limit at TMIN, TMAX Parameter All Versions Units Description t1 100 ns min CLKIN Cycle Time t2 40 ns min CLKIN High Time t3 40 ns min CLKIN Low Time t4 30 ns min FSIN Setup Time t5 30 ns min Data Setup Time t6 5 ns min Data Hold Time t6A 6 ns min LDAC Hold Time t7 90 ns max FSIN Hold Time 20 ns min t8 40 ns min LDAC, CLR Pulsewidth t9 100 ns min LDAC Setup Time NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (VIL + VIH)/2. Specifications subject to change without notice. CLKIN(I) FSIN(I) SDIN(I) DB15 t 2 t 3 t 7 t 8 CLR LDAC1 t 5 t 6A t 1 t 9 t 8 t 4 t 5 t 6 DB0 1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. LDAC2 Figure 1. Timing Diagram for AD7804 and AD7808 AD7804/AD7808 TIMING CHARACTERISTICS1 |
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