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ADC083000 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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ADC083000 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 48 page GND VA 50k 50k GND VA 50k 50k 200k 8 pF GND VA GND VA 50k 50k 200k 8 pF VA SDATA DDR GND VA 50k ADC083000 SNAS358N – JUNE 2006 – REVISED JULY 2009 www.ti.com Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude / Serial Interface Clock (Input):LVCMOS Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See The LVDS 3 OutV / SCLK Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. Edge Select / Double Data Rate / Serial Data (Input):LVCMOS This input sets the output edge of DCLK+ at which the output data transitions. (See OutEdge Setting). When OutEdge / DDR / this pin is floating or connected to 1/2 the supply voltage, DDR 4 SDATA clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. DCLK Reset (Input):LVCMOS A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See MULTIPLE 15 DCLK_RST ADC SYNCHRONIZATION for detailed description. When bit 14 in the Configuration Register (address 1h) is set to 0b, this single- ended DCLK_RST pin is selected. See also pins 22,23 description. Power Down 26 PD (Input):LVCMOS A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate (Input):LVCMOS A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin 30 CAL initiates the calibration sequence. See Calibration for an overview of self-calibration and On-Command Calibration for a description of on-command calibration. Full Scale Range Select / Extended Control Enable (Input):LVCMOS In non-extended control mode, a logic low on this pin sets the full-scale differential input range to 600 mVP-P. A logic high on this pin sets the full-scale differential input range to 820 14 FSR/ECE mVP-P. See The Analog Inputs. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See NORMAL/EXTENDED CONTROL for information on the extended control mode. Calibration Delay / Serial Interface Chip Select (Input):LVCMOS With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock 127 CalDly / SCS cycles after power up before calibration begins (See Calibration). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). 4 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Links: ADC083000 |
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