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74AUP1G02GW Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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74AUP1G02GW Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 21 page 74AUP1G02 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 27 June 2012 11 of 21 NXP Semiconductors 74AUP1G02 Low-power 2-input NOR gate [1] For measuring enable and disable times RL = 5 k Ω, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Test circuit for measuring switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 11. Test data Supply voltage Load VEXT VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
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