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ADC104S051CIMM Scheda tecnica(PDF) 6 Page - Texas Instruments |
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ADC104S051CIMM Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 25 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Track Hold Power Up Track Hold b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 9 10 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DIN DOUT Power Up SCLK CS Power Down Control register Control register DB9 DB8 DB9 DB8 ADC104S051 SNAS253G – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com ADC104S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500 ksps, , Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) VA = +3.0V −3.5 tCSU Setup Time SCLK High to CS Falling Edge See (2) 10 ns (min) VA = +5.0V −0.5 VA = +3.0V +4.5 tCLH Hold time SCLK Low to CS Falling Edge See (2) 10 ns (min) VA = +5.0V +1.5 VA = +3.0V +4 tEN Delay from CS Until DOUT active 30 ns (max) VA = +5.0V +2 VA = +3.0V +16.5 tACC Data Access Time after SCLK Falling Edge 30 ns (max) VA = +5.0V +15 tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) 0.3 x tCH SCLK High Pulse Width 0.5 x tSCLK ns (min) tSCLK 0.3 x tCL SCLK Low Pulse Width 0.5 x tSCLK ns (min) tSCLK VA = +3.0V 1.7 Output Falling VA = +5.0V 1.2 tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max) VA = +3.0V 1.0 Output Rising VA = +5.0V 1.0 (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed. Timing Diagrams Figure 1. ADC104S051 Operational Timing Diagram 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: ADC104S051 |
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