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AD7851ARS Scheda tecnica(PDF) 11 Page - Analog Devices

Il numero della parte AD7851ARS
Spiegazioni elettronici  14-Bit 333 kSPS Serial A/D Converter
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REV. B
AD7851
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.
MSB
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
2/3 MODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
LSB
Control Register Bit Function Descriptions
Bit No.
Mnemonic
Comment
13
ZERO
These four bits must be set to 0 when writing to the control register.
12
ZERO
11
ZERO
10
ZERO
9PMGT1
Power Management Bits. These two bits are used with the
SLEEP pin for putting the part into various
8PMGT0
power-down modes (see Power-Down section for more details).
7
RDSLT1
Theses two bits determine which register is addressed for the read operations. See Table II.
6
RDSLT0
52/
3 MODE
Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every
write cycle.
4
CONVST
Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati-
cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section).
3
CALMD
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
2
CALSLT1
Calibration Selection Bits and Start Calibration Bit. These bits have two functions:
1
CALSLT0
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-
0
STCAL
formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on Calibration Registers for more details).
Table III. Calibration Selection
CALMD
CALSLT1
CALSLT0
Calibration Type
00
0
A full internal calibration is initiated where the internal DAC is calibrated followed by the
internal gain error, and finally the internal offset error is calibrated out. This is the default setting.
00
1
Here the internal gain error is calibrated out followed by the internal offset error calibrated
out.
01
0This calibrates out the internal offset error only.
01
1This calibrates out the internal gain error only.
10
0
A full system calibration is initiated here where first the internal DAC is calibrated, fol-
lowed by the system gain error, and finally the system offset error is calibrated out.
10
1Here the system gain error is calibrated out followed by the system offset error.
11
0This calibrates out the system offset error only.
11
1This calibrates out the system gain error only.


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