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AD7851KRZ3 Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD7851KRZ3 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 36 page AD7851 –4– REV. B Parameter Version A 1 Version K 1 Unit Test Conditions/Comments POWER PERFORMANCE AVDD, DVDD 4.75/5.25 4.75/5.25 V min/max IDD Normal Mode 4 17 17 mA max AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA. Sleep Mode 5 With External Clock On 20 20 µA typ Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 600 600 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 300 300 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 89.25 89.25 mW max VDD = 5.25 V: Typically 63 mW; SLEEP = VDD. Sleep Mode Power Dissipation With External Clock On 105 105 µW typ VDD = 5.25 V; SLEEP = 0 V. With External Clock Off 52.5 52.5 µW max VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V. SYSTEM CALIBRATION Offset Calibration Span 6 +0.05 × V REF/–0.05 × V REF V max/min Allowable Offset Voltage Span for Calibration. Gain Calibration Span 6 +1.025 × V REF/–0.975 × V REF V max/min Allowable Full-Scale Voltage Span for Calibration. NOTES 1Temperature ranges as follows: A Version, –40 °C to +125°C; K Version, 0°C to 125°C. 2Specifications apply after calibration. 3SNR calculation includes distortion and noise components. 4All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV DD. No load on the digital outputs. Analog inputs at AGND. 5CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV DD. No load on the digital outputs. Analog inputs at AGND. 6The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V REF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × V REF). This is explained in more detail in the Calibration section of the data sheet. Specifications subject to change without notice. |
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