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74LVC2G17GW-G Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LVC2G17GW-G Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 19 page 74LVC2G17 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 8 — 2 May 2013 2 of 19 NXP Semiconductors 74LVC2G17 Dual non-inverting Schmitt trigger with 5 V tolerant input 4. Ordering information 5. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G17GW 40 Cto+125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2G17GV 40 Cto+125 C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC2G17GM 40 Cto+125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm SOT886 74LVC2G17GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm SOT891 74LVC2G17GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74LVC2G17GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 Table 2. Marking codes Type number Marking code[1] 74LVC2G17GW VV 74LVC2G17GV VV 74LVC2G17GM VV 74LVC2G17GF VV 74LVC2G17GN VV 74LVC2G17GS VV Fig 1. Logic symbol Fig 2. IEC logic symbol mnb066 1A 1Y 16 2A 2Y 34 6 1 4 3 mnb067 |
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