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TL5002IDRG4 Scheda tecnica(PDF) 3 Page - Texas Instruments

Il numero della parte TL5002IDRG4
Spiegazioni elettronici  PULSE-SIDTH-MODULATION CONTROL CIRCUIT
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TL5002IDRG4 Scheda tecnica(HTML) 3 Page - Texas Instruments

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TL5002
PULSEWIDTHMODULATION CONTROL CIRCUIT
SLVS304A − SEPTEMBER 2000 − REVISED AUGUST 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dead-time control (DTC) (continued)
R
DT +
Rt ) 1250 D Voscmax – Voscmin ) Voscmin
Where
RDT and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (CDT) as shown in Figure 2. During
soft start, the voltage at DTC is derived by the following equation:
V
DT [
I
DT
R
DT
1–e
–t R
DT
C
DT
TL5002
DTC
CDT
RDT
6
Figure 2. Soft-Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RDTCDT,
should be t0/3 to t0/5. The TL5002 remains off until VDT ≈ 0.7 V, the minimum ramp value. CDT is discharged
every time UVLO becomes active.
undervoltage-lockout (UVLO) protection
The undervoltage-lockout circuit turns the output transistor off whenever the supply voltage drops too low
(approximately 3 V at 25
°C) for proper operation. A hysteresis voltage of 200 mV eliminates false triggering on
noise and chattering.
output transistor
The output of the TL5002 is an open-collector transistor with a maximum collector current rating of 21 mA and
a voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is
lower than both the DTC voltage and the error-amplifier output voltage, and the UVLO circuit is inactive.


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TL5002ID TI-TL5002ID Datasheet
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[Old version datasheet]   PULSE-WIDTH-MODULATION CONTROL CIRCUIT
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