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ADC10664CIWMX-NOPB Scheda tecnica(PDF) 5 Page - Texas Instruments |
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ADC10664CIWMX-NOPB Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 22 page ADC10662, ADC10664 www.ti.com SNAS076E – JUNE 1999 – REVISED MARCH 2013 DC Electrical Characteristics The following specifications apply for V + = +5V, V REF(+) = 5V VREF( −) = GND, and Speed Adjust pin connected to ground through a 14.0 k Ω resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C. Units Symbol Parameter Conditions Typical(1) Limit(2) (Limits) VIN(1) Logical “1” Input Voltage V+ = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V+ = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current VIN(1) = 5V 0.005 3.0 μA (max) IIN(0) Logical “0” Input Current VIN(0) 0V −0.005 −3.0 μA (max) V+ = 4.5V, IOUT = −360 μA 2.4 V (min) VOUT(1) Logical “1” Output Voltage V+ = 4.5V, IOUT = −10 μA 4.25 V (min) VOUT(0) Logical “0” Output Voltage V+ = 4.5V, IOUT = 1.6 mA 0.4 V (max) VOUT = 5V 0.1 50 μA (max) IOUT TRI-STATE Output Current VOUT = 0V −0.1 −50 μA (max) DICC DVCC Supply Current CS = S/H = RD = 0 1.0 2 mA (max) AICC AVCC Supply Current CS = S/H = RD = 0 30 45 mA (max) (1) Typical figures represent most likely parametric norm. (2) Tested limits are ensured to AOQL (Average Outgoing Quality Level). AC Electrical Characteristics The following specifications apply for V + = +5V, t r = tf = 20 ns, VREF(+) = 5V, VREF( −) = GND, and Speed Adjust pin connected to ground through a 14.0 k Ω resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C. Units Symbol Parameter Conditions Typical(1) Limit(2) (Limits) Mode 1 Conversion Time from Rising tCONV 360 466 ns (max) Edge of S/H to Falling Edge of INT tCRD Mode 2 Conversion Time 470 610 ns (max) Access Time (Delay from Falling Edge tACC1 Mode 1; CL = 100 pF 30 50 ns (max) of RD to Output Valid) Access Time (Delay from Falling Edge tACC2 Mode 2; CL = 100 pF 475 616 ns (max) of RD to Output Valid) tSH Minimum Sample Time Mode 1 (Figure 3)(3) 150 ns (max) TRI-STATE Control (Delay from Rising t1H, t0H RL = 1k, CL = 10 pF 30 60 ns (max) Edge of RD to High-Z State) Delay from Rising Edge of RD to Rising tINTH CL = 100 pF 25 50 ns (max) Edge of INT Delay from End of Conversion to Next tP 50 ns (max) Conversion tMS Multiplexer Control Setup Time 10 75 ns (max) tMH Multiplexer Hold Time 10 40 ns (max) CVIN Analog Input Capacitance 35 pF (max) COUT Logic Output Capacitance 5 pF (max) CIN Logic Input Capacitance 5 pF (max) (1) Typical figures represent most likely parametric norm. (2) Tested limits are ensured to AOQL (Average Outgoing Quality Level). (3) Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs. tSH. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC10662 ADC10664 |
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