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ADC084S101 Scheda tecnica(PDF) 5 Page - Texas Instruments |
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ADC084S101 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 27 page ADC124S101 www.ti.com SNAS283D – MARCH 2005 – REVISED MARCH 2013 ADC124S101 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 to 16 MHz, fSAMPLE = 500 ksps to 1 Msps, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(2) Units COUT TRI-STATE Output Capacitance 2 4 pF (max) Output Coding Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) 2.7 V (min) VA Supply Voltage 5.25 V (max) VA = +5.25V, 2.5 3.0 mA (max) fSAMPLE = 1 Msps, fIN = 40 kHz Supply Current, Normal Mode (Operational, CS low) VA = +3.6V, 1.2 1.6 mA (max) fSAMPLE = 1 Msps, fIN = 40 kHz IA VA = +5.25V, 60 nA fSAMPLE = 0 ksps Supply Current, Shutdown (CS high) VA = +3.6V, 38 nA fSAMPLE = 0 ksps VA = +5.25V 13.1 15.8 mW (max) Power Consumption, Normal Mode (Operational, CS low) VA = +3.6V 4.3 5.8 mW (max) PD VA = +5.25V 0.32 µW Power Consumption, Shutdown (CS high) VA = +3.6V 0.14 µW AC ELECTRICAL CHARACTERISTICS 8 MHz (min) fSCLK Maximum Clock Frequency See(3) 16 MHz (max) 500 ksps (min) fS Sample Rate See(3) 1 Msps (max) tCONV Conversion Time 13 SCLK cycles 30 % (min) DC SCLK Duty Cycle fSCLK = 16 MHz 50 70 % (max) tACQ Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles (3) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is specified under Operating Ratings. ADC124S101 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 Msps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(1) Units VA = +3.0V −3.5 tCSU Setup Time SCLK High to CS Falling Edge See(2) 10 ns (min) VA = +5.0V −0.5 VA = +3.0V +4.5 tCLH Hold time SCLK Low to CS Falling Edge See(2) 10 ns (min) VA = +5.0V +1.5 VA = +3.0V +4 tEN Delay from CS Until DOUT active 30 ns (max) VA = +5.0V +2 VA = +3.0V +14.5 tACC Data Access Time after SCLK Falling Edge 30 ns (max) VA = +5.0V +13 tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) (1) Tested limits are specified to AOQL (Average Outgoing Quality Level). (2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC124S101 |
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