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SN74CBTLV16212DGGR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74CBTLV16212DGGR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 13 page SN74CBTLV16212 LOW VOLTAGE 24BIT FET BUSEXCHANGE SWITCH SCDS044I − DECEMBER 1997 − REVISED OCTOBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus Family D 4-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports D Ioff Supports Partial-Power-Down Mode Operation D Break-Before-Make Feature D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information The SN74CBTLV16212 provides 24 bits of high-speed bus switching or exchanging. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device operates as a 24-bit bus switch or a 12-bit bus exchanger, which provides data exchanging between the four signal ports via the data-select (S0, S1, S2) terminals. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. The SN74CBTLV16212 is specified by the break-before-make feature to have no through current when switching between B ports. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP − DL Tube SN74CBTLV16212DL CBTLV16212 −40 °C to 85°C SSOP − DL Tape and reel SN74CBTLV16212DLR CBTLV16212 −40 °C to 85°C TSSOP − DGG Tape and reel SN74CBTLV16212GR CBTLV16212 TVSOP − DGV Tape and reel SN74CBTLV16212VR CN212 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated DGG, DGV, OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 S0 1A1 1A2 2A1 2A2 3A1 3A2 GND 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 VCC 8A1 GND 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 S1 S2 1B1 1B2 2B1 2B2 3B1 GND 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 GND 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. |
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