ADF4154BRU-REEL datasheet(3/24 Pages) AD

Il numero della parte	ADF4154BRU-REEL

Spiegazioni elettronici	Fractional-N Frequency Synthesizer

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Data Sheet

ADF4154

Rev. C | Page 3 of 24

SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm

referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.

Table 1.

Parameter

B Version

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

See

Figure 15 for the input circuit.

RF Input Frequency (RFIN)1

0.5/4.0

GHz min/max

−8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/µs.

1.0/4.0

GHz min/max

−10 dBm/0 dBm min/max.

REFERENCE CHARACTERISTICS

See

Figure 14 for input circuit.

REFIN Input Frequency1

10/250

MHz min/max

For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave,

slew rate > 25 V/µs.

REFIN Input Sensitivity

0.7/AVDD

V p-p min/max

Biased at AVDD/2.2

REFIN Input Capacitance

10

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency3

32

MHz max

CHARGE PUMP

ICP Sink/Source

Programmable. See

Table 5.

High Value

5

mA typ

With RSET = 5.1 kΩ.

Low Value

312.5

µA typ

Absolute Accuracy

2.5

% typ

With RSET = 5.1 kΩ.

RSET Range

2.7/10

kΩ min/max

ICP Three-State Leakage Current

1

nA typ

Sink and source current.

Matching

2

% typ

0.5 V < VCP < VP − 0.5 V.

ICP vs. VCP

2

% typ

0.5 V < VCP < VP − 0.5 V.

ICP vs. Temperature

2

% typ

VCP = VP/2.

LOGIC INPUTS

VINH, Input High Voltage

1.4

V min

VINL, Input Low Voltage

0.6

V max

IINH/IINL, Input Current

±1

µA max

CIN, Input Capacitance

10

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

V min

Open-drain 1 kΩ pull-up to 1.8 V.

VOL, Output Low Voltage

0.4

V max

IOL = 500 µA.

POWER SUPPLIES

AVDD

2.7/3.3

V min/V max

DVDD, SDVDD

AVDD

VP

AVDD/5.5

V min/V max

IDD

24

mA max

20 mA typical.

Low Power Sleep Mode

1

µA typ

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PNSYNTH)4

−220

dBc/Hz typ

PLL loop BW = 500 kHz.

Measured at 100 kHz offset.

Normalized 1/f Noise (PN1_f)5

−114

dBc/Hz typ

10 kHz offset; normalized to 1GHz.

Phase Noise Performance6

@ VCO output.

1750 MHz Output7

−102

dBc/Hz typ

@ 1 kHz offset, 26 MHz PFD frequency.

1

Use a square wave for frequencies below fMIN.

2

AC coupling ensures AVDD/2 bias. See Figure 14 for a typical circuit.

3

Guaranteed by design. Sample tested to ensure compliance.

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,

and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

6

The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer.

7

fREFIN = 26 MHz, fPFD = 26 MHz, offset frequency = 1 kHz, RFOUT = 1750 MHz, loop B/W = 20 kHz, lowest noise mode.

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