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AD7893AR-3 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD7893AR-3 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 12 page AD7893 –7– REV. E Track/Hold Section The track/hold amplifier on the analog input of the AD7893 allows the ADC to accurately convert an input sine wave of full- scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate of 117 kHz (i.e., the track/hold can handle input frequencies in excess of 58 kHz). The track/hold amplifier acquires an input signal to 12-bit accu- racy in less than 1.5 µs. The operation of the track/hold is essen- tially transparent to the user. The track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion (i.e., the rising edge of CONVST). The aperture time for the track/hold (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns. At the end of conversion (6 µs after the rising edge of CONVST ) the part returns to its tracking mode. The acquisi- tion time of the track/hold amplifier begins at this point. Reference Input The reference input to the AD7893 is a buffered on-chip with a maximum reference input current of 1 µA. The part is specified with a +2.5 V reference input voltage. Errors in the reference source will result in gain errors in the AD7893’s transfer func- tion and will add to the specified full-scale errors on the part. On the AD7893-10 it will also result in an offset error injected in the attenuator stage. Suitable reference sources for the AD7893 include the AD780 and AD680 precision +2.5 V references. Timing and Control Section Figure 3 shows the timing and control sequence required to ob- tain optimum performance from the AD7893. In the sequence shown, conversion is initiated on the rising edge of CONVST, and new data from this conversion is available in the output reg- ister of the AD7893 6 µs later. Once the read operation has taken place, a further 600 ns should be allowed before the next rising edge of CONVST to optimize the settling of the track/ hold amplifier before the next conversion is initiated. With the serial clock frequency at its maximum of 8.33 MHz, the achiev- able throughput rate for the part is 6 µs (conversion time) plus 1.92 µs (read time) plus 0.6 µs (acquisition time). This results in a minimum throughput time of 8.52 µs (equivalent to a through- put rate of 117 kHz). The read operation consists of sixteen serial clock pulses to the output shift register of the AD7893. After sixteen serial clock pulses the shift register is reset and the SDATA line is three- stated. If there are more serial clock pulses after the sixteenth clock, the shift register will be moved on past its reset state; however, the shift register will be reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle. As a result, a read operation from the output register should not straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation, and the data read back into the microprocessor will appear invalid. The throughput rate of the part can be increased by reading data during conversion. If the data is read during conversion, a throughput time of 6 µs (conversion time) plus 1.5 µs is achieved. This minimum throughput time of 7.5 µs is achieved with a slight reduction in performance from the AD7893. The signal to (noise + distortion) number is likely to degrade by ap- proximately 1.5 dB while the code flicker from the part will also increase (see AD7893 PERFORMANCE section). Because the AD7893 is provided in an 8-pin package to mini- mize board space, the number of pins available for interfacing is very limited. As a result, no status signal is provided from the AD7893 to indicate when conversion is complete. In many applications, this will not be a problem as the data can be read from the AD7893 during conversion or after conversion; how- ever, applications that want to achieve optimum performance from the AD7893 will have to ensure that the data read does not occur during conversion or during 600 ns prior to the rising edge of CONVST. This can be achieved in two ways. The first is to ensure in software that the read operation is not initiated until 6 µs after the rising edge of CONVST. This will only be possible if the software knows when the CONVST command is issued. The second scheme would be to use the CONVST sig- nal as both the conversion start signal and an interrupt signal. The simplest way to do this would be to generate a square wave signal for CONVST with high and low times of 6 µs (see Figure 4). Conversion is initiated on the rising edge of CONVST. The falling edge of CONVST occurs 6 µs later and can be used as ei- ther an active low or falling, edge-triggered interrupt signal to tell the processor to read the data from the AD7893. Provided that the read operation is completed 600 ns before the rising edge of CONVST, the AD7893 will operate to specification. CONVST SCLK CONVERSION IS INITIATED AND TRACK/HOLD GOES INTO HOLD t1 CONVERSION ENDS 6µs LATER SERIAL READ OPERATION OUTPUT SERIAL SHIFT REGISTER IS RESET 600ns MIN tCONVERT READ OPERATION SHOULD END 600ns PRIOR TO NEXT RISING EDGE OF CONVST Figure 3. Timing Sequence for Optimum Performance from the AD7893 |
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