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ADF4360-1BCPZRL Scheda tecnica(PDF) 11 Page - Analog Devices |
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ADF4360-1BCPZRL Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 24 page Data Sheet ADF4360-1 Rev. C | Page 11 of 24 After band select, normal PLL action resumes. The nominal value of KV is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been selected (by programming DIV2 [DB22], high in the N counter latch). The ADF4360 family contains linearization circuitry to min- imize any variation of the product of ICP and KV. The operating current in the VCO core is programmable in four steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by Bits PC1 and PC2 in the control latch. OUTPUT STAGE The RFOUTA and RFOUTB pins of the ADF4360 family are con- nected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 15. To allow the user to optimize the power dissipation versus the output power requirements, the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch. Four current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give output power levels of −13 dBm, −10.5 dBm, −8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to VDD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). If the outputs are used individually, the optimum output stage consists of a shunt inductor to VDD. Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch. VCO RFOUTA RFOUTB BUFFER/ DIVIDE BY 2 Figure 15. Output Stage ADF4360-1 |
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