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AD7896AR-REEL Scheda tecnica(PDF) 8 Page - Analog Devices

Il numero della parte AD7896AR-REEL
Spiegazioni elettronici  2.7 V to 5.5 V, 12-Bit, 8 s ADC in 8-Lead SOIC/PDIP
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

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AD7896
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 2 is for optimum performance in
Operating Mode 1 where the falling edge of
CONVST starts the
conversion and puts the track-and-hold amplifier into its hold
mode. This falling edge of
CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 8
µs max after the falling edge of CONVST, and new
data from this conversion is available in the output register of
the AD7896. A read operation accesses this data. This read
operation consists of 16 clock cycles, and the length of this read
operation depends on the serial clock frequency. For the fastest
throughput rate (with a serial clock of 10 MHz at 5 V opera-
tion), the read operation will take 1.6
µs. The read operation
must be complete at least 400 ns before the falling edge of
the next
CONVST, which gives a total time of 10
µs for the full
throughput time (equivalent to 100 kHz). This mode of opera-
tion should be used for high sampling applications.
Mode 2 Operation (Auto Sleep after Conversion)
The timing diagram in Figure 3 is for optimum performance in
Operating Mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes up”
tCONVERT = 8 s
BUSY
SCLK
SERIAL READ
OPERATION
CONVERSION ENDS
8 s LATER
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
CONVERSION IS
INITIATED AND
TRACK-AND-HOLD GOES
INTO HOLD
t1 = 40ns MIN
400ns MIN
t1
tCONVERT = 8 s
READ OPERATION
SHOULD END 400ns
PRIOR TO NEXT
FALLING EDGE OF
CONVST
CONVST
Figure 2. Mode 1 Timing Operation Diagram for High Sampling Performance
CONVST
BUSY
SCLK
SERIAL READ
OPERATION
CONVERSION
ENDS
14µs LATER
READ OPERATION
SHOULD END 400ns
PRIOR TO NEXT
FALLING EDGE OF
CONVST
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
PART
WAKES
UP
CONVERSION
IS INITIATED
TRACK-AND-
HOLD GOES
INTO HOLD
t1 = 6 s
WAKE-UP
TIME
t1
tCONVERT = 14 s
400ns MIN
Figure 3. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
before the next conversion takes place. This is achieved by
keeping
CONVST low at the end of conversion, whereas it was
high at the end of conversion for Mode 1 operation. The rising
edge of
CONVST “wakes up” the part. This wake-up time is 6
µs, at which point the track-and-hold amplifier goes into its hold
mode. The conversion takes 8
µs after this, provided the
CONVST has gone low, giving a total of 14
µs from the rising
edge of
CONVST to the conversion being complete, which is
indicated by the BUSY going low. Note that since the wake-
up time from the rising edge of
CONVST is 6
µs, when the
CONVST pulsewidth is greater than 6
µs, the conversion will
take more than the 14
µs shown in the diagram from the rising
edge of
CONVST. This is because the track-and-hold amplifier
goes into its hold mode on the falling edge of
CONVST and
then the conversion will not be complete for a further 8
µs. In
this case, the BUSY will be the best indicator for when the
conversion is complete. Even though the part is in sleep mode,
data can still be read from the part. The read operation consists
of 16 clock cycles as in Mode 1 operation. For the fastest serial
clock of 10 MHz at 5 V operation, the read operation will take
1.6
µs, which must be complete at least 400 ns before the falling
edge of the next
CONVST to allow the track-and-hold amplifier
to have enough time to settle. This mode is very useful when the
part is converting at a slow rate as the power consumption will
be significantly reduced from that of Mode 1 operation.
Rev. D


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AD7896AR-REEL AD-AD7896AR-REEL Datasheet
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   2.7 V to 5.5 V, 12-Bit ADC in 8-Lead SOIC/PDIP
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