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AD5246BKSZ10-R2 Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD5246BKSZ10-R2 Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 16 page Data Sheet AD5246 Rev. C | Page 5 of 16 TIMING CHARACTERISTICS VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ1 Max Unit I2C INTERFACE TIMING CHARACTERISTICS2, 3, 4 SCL Clock Frequency fSCL 400 kHz tBUF Bus Free Time Between STOP and START t1 1.3 µs tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated 0.6 µs tLOW Low Period of SCL Clock t3 1.3 µs tHIGH High Period of SCL Clock t4 0.6 50 µs tSU;STA Setup Time for Repeated START Condition t5 0.6 µs tHD;DAT Data Hold Time t6 0.9 µs tSU;DAT Data Setup Time t7 100 ns tF Fall Time of Both SDA and SCL Signals t8 300 ns tR Rise Time of Both SDA and SCL Signals t9 300 ns tSU;STO Setup Time for STOP Condition t10 0.6 µs 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design; not subject to production test. 3 See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values. 4 Specifications apply to all parts. |
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