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CDCLVD110AVFRG4 Scheda tecnica(PDF) 6 Page - Texas Instruments

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Il numero della parte CDCLVD110AVFRG4
Spiegazioni elettronici  PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDCLVD110AVFRG4 Scheda tecnica(HTML) 6 Page - Texas Instruments

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CDCLVD110A
SCAS841C – FEBRUARY 2007 – REVISED NOVEMBER 2009
www.ti.com
SPECIFICATION OF CONTROL REGISTER
The CDCLVD110A has an 11-bit, serial-in shift register and an 11-bit control register. The control Register
enables/disables each output clock, and selects either CLK0 or CLK1 as the input clock. The CDCLVD110A has
two modes of operation:
Programmable Mode (EN=1)
The shift register uses a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11
clock pulses, the 12th clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9-Q9
output pair, and the 10th bit (bit 9) enables the Q0-Q0 pair. The 11th bit (bit 10) on SI selects either CLK0 or
CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To restart the
control register configuration, a reset of the state machine must be done with a clock pulse on CK (shift
register clock input) and EN set to low. The control register can be configured only once after each reset.
Standard Mode (EN=0)
In this mode, the CDCLVD110A is not programmable and all the clock outputs are enabled. The clock input
(CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register.
STATE-MACHINE INPUTS
EN
SI
CK
OUTPUT
L
L
X
All outputs enabled, CLK0 selected, control register disabled, default state
L
H
X
All outputs enabled, CLK1 selected, control register disabled
H
L
First stage stores L, other stage stores data of previous stage
H
H
First stage stores H, other stage stores data of previous stage
L
X
Reset of state machine, shift and control registers
CONTROL REGISTER
BIT 10
BITS [0-9]
QN[0-9]
L
H
CLK0
H
H
CLK1
X
L
Outputs disabled
SERIAL INPUT (SI) SEQUENCE
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CLK_SEL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
TRUTH TABLE FOR CONTROL LOGIC
CK
EN
SI
CLK0
CLK0
CLK1
CLK1
Q(0-9)
Q(0-9)
L
L
L
L
H
X
X
L
H
L
L
L
H
L
X
X
H
L
L
L
L
Open
Open
X
X
L
H
L
L
H
X
X
L
H
L
H
L
L
H
X
X
H
L
H
L
L
L
H
X
X
Open
Open
L
H
All outputs enabled
X = Don't care
6
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD110A


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