ADF4107

Data Sheet

Rev. D | Page 6 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CP

CPGND

AGND

1

2

3

4

5

6

7

8

MUXOUT

LE

DATA

CLK

CE

DGND

16

15

14

13

12

11

10

9

TOP VIEW

(Not to Scale)

ADF4107

NOTES:

1. TRANSISTOR COUNT 6425 (CMOS),

303 (BIPOLAR).

Figure 3. Pin Configuration, TSSOP

14

13

12

1

3

4

LE

15 MUXOUT

DATA

CLK

11 CE

CPGND

AGND

2

AGND

5

ADF4107

TOP VIEW

(Not to Scale)

NOTES

1. TRANSISTOR COUNT 6425 (CMOS),

303 (BIPOLAR).

2. THE EXPOSED PAD MUST BE

CONNECTED TO AGND.

Figure 4. Pin Configuration, LFCSP

Table 4. Pin Function Descriptions

Pin No.

TSSOP

LFCSP

Mnemonic

Description

1

19

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The

SET

MAX

CP

R

I

5

.

25

=

2

20

CP

the external VCO.

3

1

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

4

2, 3

AGND

Analog Ground. This is the ground return path of the prescaler.

5

4

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 18.

6

5

Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

7

6, 7

Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog

8

8

resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can

be ac-coupled.

9

9, 10

DGND

Digital Ground.

10

11

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2.

11

12

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

12

13

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.

13

14

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

14

15

MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to

be accessed externally.

15

16, 17

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground

16

18

can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.

EP

Exposed Pad. The exposed pad must be connected to AGND.