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Si5475DC Scheda tecnica(PDF) 2 Page - Texas Instruments |
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Si5475DC Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 29 page TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION(1) PRODUCT VOUT Buck1: Adjustable TPS75003MRHLREP Buck2: Adjustable LDO: Adjustable (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document or see the Texas Instruments website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPS75003 UNIT VINX range (IN1, IN2, IN3) -0.3 to +7 V VENX range (EN1, EN2, EN3) -0.3 to VINX + 0.3 V VSWX range (SW1, SW2, SW3) -0.3 to VINX + 0.3 V VISX range (IS1, IS2, IS3) -0.3 to VINX + 0.3 V VOUT3 range -0.3 to +7 V VSSX range (SS1, SS2, SS3) -0.3 to VINX + 0.3 V VFBX range (FB1, FB2, FB3) -0.3 to +3.3 V Peak LDO output current (IOUT3) Internally limited — Continuous total power dissipation See the Thermal Information Table — Junction temperature range, TJ -55 to +150 °C Storage temperature range -65 to +150 °C ESD rating, HBM 1 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP |
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