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FDC37C669-MT Scheda tecnica(PDF) 9 Page - Microchip Technology

Il numero della parte FDC37C669-MT
Spiegazioni elettronici  PC 98/99 Compliant Super I/O Floppy Disk Controller
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
81,91
nRequest to
Send
(System Option)
nRTS1
nRTS2
(SYSOPT)
O4
Active low Request to Send outputs for the
Serial Port. Handshake output signal notifies
modem that the UART is ready to transmit
data.
This signal can be programmed by
writing to bit 1 of Modem Control Register
(MCR).
The hardware reset will reset the
nRTS signal to inactive mode (high). Forced
inactive during loop mode operation.
At the trailing edge of hardware reset, the
nRTS2 input is latched to determine the
configuration base address.
0 : INDEX Base I/O Address = 3F0 Hex
1 : INDEX Base I/O Address = 370 Hex
83,93
nData Terminal
Ready
nDTR1
nDTR2
O4
Active low Data Terminal Ready outputs for
the serial port.
Handshake output signal
notifies modem that the UART is ready to
establish data communication link. This signal
can be programmed by writing to bit 0 of
Modem
Control
Register
(MCR).
The
hardware reset will reset the nDTR signal to
inactive mode (high). Forced inactive during
loop mode operation.
82,92
nClear to Send
nCTS1
nCTS2
I
Active low Clear to Send inputs for the serial
port.
Handshake signal which notifies the
UART that the modem is ready to receive
data.
The CPU can monitor the status of
nCTS signal by reading bit 4 of Modem Status
Register (MSR). A nCTS signal state change
from low to high after the last MSR read will
set MSR bit 0 to a 1.
If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nCTS changes state.
The
nCTS signal has no effect on the transmitter.
Note:
Bit 4 of MSR is the complement of
nCTS.


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