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SI3050-E-GT Scheda tecnica(PDF) 8 Page - Silicon Laboratories

Il numero della parte SI3050-E-GT
Spiegazioni elettronici  PCM highway data interface law A-law companding SPI control interface GCl interface
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SI3050-E-GT Scheda tecnica(HTML) 8 Page - Silicon Laboratories

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Si3050 + Si3018/19
8
Rev. 1.31
Table 4. AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for F/K-Grade, Fs = 8000 Hz, see "2. Typical Application Schematic" on page 17)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Sample Rate
Fs
8
16
kHz
PCLK Input Frequency
PCLK
256
8192
kHz
Receive Frequency Response
Low –3 dBFS Corner, FILT = 0
5
Hz
Receive Frequency Response
Low –3 dBFS Corner, FILT = 1
200
Hz
Transmit Full-Scale Level1
VFS
FULL = 0 (0 dBm)
1.1
VPEAK
FULL = 1 (+3.2 dBm)2
—1.58
VPEAK
FULL2=1(+6.0 dBm)2
—2.16
VPEAK
Receive Full-Scale Level1,3
VFS
FULL = 0 (0 dBm)
1.1
VPEAK
FULL = 1 (+3.2 dBm)2
—1.58
VPEAK
FULL2=1(+6.0 dBm)2
—2.16
VPEAK
Dynamic Range4,5,6
DR
ILIM = 0, DCV = 11, MINI=00
DCR = 0, IL =100 mA
—80
dB
Dynamic Range4,5,6
DR
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL =20mA
—80
dB
Dynamic Range4,5,6
DR
ILIM = 1, DCV = 11, MINI=00
DCR = 0, IL =50mA
—80
dB
Transmit Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 11, MINI=00
DCR = 0, IL =100 mA
—–72
dB
Transmit Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL =20mA
—–78
dB
Receive Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL =20mA
—–78
dB
Receive Total Harmonic
Distortion6,7
THD
ILIM = 1,DCV = 11, MINI=00
DCR = 0, IL =50mA
—–78
dB
Notes:
1. Measured at TIP and RING with 600
termination at 1 kHz, as shown in Figure 1 on page 6.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600
 ac termination. While
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved with a
600
 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes harmonics.
Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin=1kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 10–11 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.


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