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74LVC1G07GW-Q100 Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LVC1G07GW-Q100 Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 13 page 74LVC1G07_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 23 May 2013 2 of 13 NXP Semiconductors 74LVC1G07-Q100 Buffer with open-drain output 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 6. Pinning information 6.1 Pinning Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G07GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G07GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 Table 2. Marking Type number Marking code[1] 74LVC1G07GW-Q100 VS 74LVC1G07GV-Q100 V07 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna623 AY 2 4 mna624 4 2 A Y mna591 Y A GND Fig 4. Pin configuration SOT353-1 and SOT753 |
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