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ML2004IP Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor

Il numero della parte ML2004IP
Spiegazioni elettronici  Logarithmic Gain/Attenuator
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

ML2004IP Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor

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ML2003, ML2004
PRODUCT SPECIFICATION
2
REV. 1.1.1 3/19/01
Pin Description
Absolute Maximum Ratings1
Name
Function
C3
In serial mode, pin is unused. In parallel mode, coarse gain select bit. Pin has internal pulldown
resistor to GND.
(LATI) C2
In serial mode, input latch clock which loads the data from the shift register into the latch.
In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
(SID) C1
In serial mode, serial data input that contains serial 9 bit data word which controls the gain
setting. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
(LATO) C0
In serial mode, output latch clock which loads the 9 bit data word back into the shift register from
the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
PDN
Powerdown input. When PDN = 1, device is in powerdown mode. When PDN = 0, device is in
normal operation. Pin has internal pulldown resistor to GND.
F3
In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown
resistor to GND.
(SCK) F2
In serial mode, shift register clock which shifts the serial data on SID into the shift register on
rising edges and out on SOD on falling edges. In parallel mode, fine gain select bit. Pin has
internal pulldown resistor to GND.
F1
In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown
resistor to GND.
GND
Digital ground. 0 volts. All digital inputs and outputs are referenced to this ground.
SER/PAR
Serial or parallel select input. When SER/PAR = 1, device is in serial mode.
When SER/PAR = 0, device is in parallel mode. Pin has internal pullup resistor to VCC.
(SOD) F0
In serial mode, serial output data which is the output of the shift register. In parallel mode, fine
gain select bit. Pin has internal pulldown resistor to GND.
VIN
Analog input.
AGND
Analog ground. 0 volts. Analog input and output are referenced to this ground.
VSS
Negative supply. –5 volts ±10%.
VOUT
Analog output.
VCC
Positive supply. +5 volts ±10%.
ATTEN/GAIN
In serial mode, pin is unused. In parallel mode, attenuation/gain select bit. Pin has internal
pulldown resistor to GND.
Parameter
Min.
Max.
Units
Supply Voltage
VCC
VSS
+6.5
-6.5
V
V
AGND with respect to GND
±0.5
V
Analog Input and Output
VSS –0.3V
VCC +0.3
V
Digital Input and Outputs
GND –0.3
VCC +0.3
V
Input Current Per Pin
±25
mA
Power Dissipation
750
mW
Storage Temperature Range
-65
+150
°C
Lead Temeperature (Soldering, 10 sec)
300
°C


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