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74LCX74MTC Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74LCX74MTC Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.0 2 Connection Diagrams Pin Assignments for SOIC, SOP, and TSSOP Pad Assignment for DQFN (Top View) Pin Description Logic Symbols IEEE/IEC Truth Table (Each Half) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs Inputs Outputs SD CD CP D Q Q LH X X HL HL X X LH LL X X H H HH H H L HH L L H HH L X Q0 Q0 |
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