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AZP92NAG Scheda tecnica(PDF) 2 Page - Arizona Microtek, Inc |
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AZP92NAG Scheda tecnica(HTML) 2 Page - Arizona Microtek, Inc |
2 / 8 page Arizona Microtek, Inc. AZP92 PECL/ECL ÷1, ÷2 Clock Generation Chip with Selectable Enable www.azmicrotek.com +1-480-962-5881 2 Request a Sample Aug 2013, Rev 2.1 PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin Name Type Function 1 EN-SEL Input Enable Polarity Select 2 D Input Data Input 3 VBB Input Reference Voltage 4 EN Input Output Enable 5 DIV-SEL Input Divide Select 6 Q ¯ Output Inverted PECL Output 7 Q Output PECL Output 8 VCC Power Positive Supply 9 VEE Power Negative Supply D 4 3 2 1 6 5 8 7 EN Q VCC VEE EN-SEL Q DIV-SEL VBB Figure 1 - Pin Configuration |
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