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AZP52 Scheda tecnica(PDF) 4 Page - Arizona Microtek, Inc

Il numero della parte AZP52
Spiegazioni elettronici  Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator
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Produttore elettronici  AZM [Arizona Microtek, Inc]
Homepage  http://azmicrotek.com
Logo AZM - Arizona Microtek, Inc

AZP52 Scheda tecnica(HTML) 4 Page - Arizona Microtek, Inc

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Arizona Microtek, Inc.
AZP52
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
www.azmicrotek.com
+1-480-962-5881
4
Request a Sample
Mar 2013, Rev 2.2
INPUT TERMINATION
The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mVpp ensures the AZP52 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.
D
VDD/2
10k
Input signal
A/R
Figure 3 - Input Termination
OUTPUT TERMINATION TECHNIQUES
The LVPECL compatible output stage of the AZP52 uses a current drive topology to maximize switching speed as
illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS
current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output
current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output
voltage swings match LVPECL levels when external 50
Ω resistors terminate the outputs.
Both Q and Q
¯ should always be terminated identically to avoid waveform distortion and circulating current caused by
unsymmetrical loads. This rule should be followed even if only one output is in use.
VDD (+3.3 V)
Vbp
M1
M2
M3
M4
D
Vbn
M5
21.1mA
21.1mA
16mA
VTT = VDD - 2.0V
Q
Q
50
50
21.1mA - High
5.1mA - Low
External
Circuitry
Output
Stage
Figure 4 - Typical Output Termination


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