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KM4170IT5TR3 Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor |
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KM4170IT5TR3 Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor |
8 / 16 page DATA SHEET KM4170, KM4270, KM4470 8 REV. 5 December 2002 Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: • Include 6.8 µF and 0.01µF ceramic capacitors • Place the 6.8 µF capacitor within 0.75 inches of the power pin • Place the 0.01 µF capacitor within 0.1 inches of the power pin • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance • Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 6 for more information. When evaluating only one channel, complete the following on the unused channel: 1. Ground the non-inverting input 2. Short the output to the inverting input Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Evaluation board schematics are shown in Figures 5a, 5b, 5c and layouts are shown in Figure 6a through Figure 6l. Figure 5a: KM4170 Evaluation Board Schematic Eval Bd Description Products KEB002 Single Channel, Dual Supply, KM4170IT5 5 and 6 lead SOT23 KEB011 Single Channel, Dual Supply, KM4170IS5 5 and 6 lead SC70 KEB006 Dual Channel, Dual Supply, KM4270IC8 8 lead SOIC KEB010 Dual Channel, Dual Supply, KM4270IM8 8 lead MSOP KEB012 Quad Channel, Dual Supply, KM4470IP14 14 lead TSSOP Figure 5b: KM4270 Evaluation Board Schematic |
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