74ABT125_4

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Product data sheet

Rev. 04 — 27 April 2010

2 of 15

NXP Semiconductors

74ABT125

Quad buffer; 3-state

4.

Functional diagram

5.

Pinning information

5.1 Pinning

5.2 Pin description

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one buffer)

mna228

1A

1Y

2

1

3

1OE

2A

2Y

5

4

6

2OE

3A

3Y

9

10

8

3OE

4A

4Y

12

13

11

4OE

mna229

1

EN1

1

3

2

4

6

5

10

8

9

13

11

12

mna227

nOE

nA

nY

Fig 4.

Pin configuration DIP14, SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

74ABT125

1OE

1A

4OE

1Y

4A

2OE

4Y

2A

3OE

2Y

3A

GND

3Y

001aai027

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aai028

74ABT125

Transparent top view

2Y

3A

2A

3OE

2OE

4Y

1Y

4A

1A

4OE

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

1OE to 4OE

1, 4, 10, 13

output enable input (active LOW)

1A to 4A

2, 5, 9, 12

data input

1Y to 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

14

supply voltage