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74HC74BQ Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74HC74BQ Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 21 page 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 27 August 2012 7 of 21 NXP Semiconductors 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max 74HC74 tpd propagation delay nCP to nQ, nQ; see Figure 7 [2] VCC = 2.0 V - 47 220 - 265 ns VCC = 4.5 V - 17 44 - 53 ns VCC =5V; CL =15pF - 14 - - - ns VCC = 6.0 V - 14 37 - 45 ns nSD to nQ, nQ; see Figure 8 [2] VCC = 2.0 V - 50 250 - 300 ns VCC = 4.5 V - 18 50 - 60 ns VCC =5V; CL =15pF - 15 - - - ns VCC = 6.0 V - 14 43 - 51 ns nRD to nQ, nQ; see Figure 8 [2] VCC = 2.0 V - 52 250 - 300 ns VCC = 4.5 V - 19 50 - 60 ns VCC =5V; CL =15pF - 16 - - - ns VCC = 6.0 V - 15 43 - 51 ns tt transition time nQ, nQ; see Figure 7 [3] VCC = 2.0 V - 19 95 - 110 ns VCC = 4.5 V - 7 19 - 22 ns VCC = 6.0 V - 6 16 - 19 ns tW pulse width nCP HIGH or LOW; see Figure 7 VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns nSD, nRD LOW; see Figure 8 VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns trec recovery time nSD, nRD; see Figure 8 VCC = 2.0 V 40 3 - 45 - ns VCC = 4.5 V 8 1 - 9 - ns VCC = 6.0 V 7 1 - 8 - ns |
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