KA7630/KA7631

3

°C, unless otherwise specified)

Notes:

1. To check the reset circuit ,the reset output is low to discharge the delay capacitor(=Cd). if it’s less than Vo1-0.25V. And the

reset output is high when the delay capacitor voltage linearly increased by the internal current source(10

µA) if it’s more than

Vo1- 0.2V. The equation of delay time is same as below. Trd = (Cd × 2.5) / 10

µA

2. These parameters, although guaranteed, are not 100% tested in production.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Output Voltage 1

Vo1

Io1 = 10mA

7.5V < Vin1 < 14V

5mA < Io1 < 500mA

5

4.9

5.1

5.1

5.2

5.3

V

Output Voltage 2

Vo2

Io2 = 10mA

11.5V < Vin2 < 18V

5mA < Io2< 500mA

8.82

8.65

9

9

9.18

9.35

V

Dropout Output Voltage 1,2

Vd1,2

Io1,2 = 500mA

-

-

2.5

V

Line Regulation 1,2

∆Vo 1,2

7.5V < Vin1< 14V

11.5V < Vin2< 18V

Io1,2 = 200mA

--

50

80

mV

Load Regulation 1,2

∆Vo 1,2

5mA < Io1< 500mA

5mA < Io2 < 500mA

--

100

160

mV

Output Voltage 3

Vo3

Vsys =13V, Io3 = 100mA

11.7

12

12.3

V

Line Regulation 3

∆Vo3

13V < Vin2 <18V, Io3 =100mA

-

-

120

mV

Load Regulation 3

∆Vo3

5mA < Io3 < 1A

-

-

250

mV

Reset Pulse Delay

Trd

Cd = 100nF, Note1

-

25

-

ms

Saturation Voltage in Reset

Condition

VrL

I6 = 5mA

-

-

0.4

V

Leakage Current at Pin 6

IrH

V6 = 10V

-

-

10

µA

Output Voltage Thermal Drift

STt

0

°C < Tj < +125°C , Note2

-

100

-

ppm/

°C

Short Circuit Output Current

Isc1,2

Vin1 = 7.5V ,Vin2 = 11.5V

-

-

1.6

A

Disable Voltage High

VdisH

Output 2 Active

0.8

-

2.0

V

Disable Voltage Low

VdisL

Output 2 Disabled

0.8

-

2.0

V

Disable Bias Current

Idis

0V < Vdis < 7V

-100

-

2

µA

Junction Temperature for TSD

Ttsd

Note2

-

145

-

°C

Quiescent Current

Iq

Io1=10mA, Output2 Disabled

-

-

2

mA

Reset Threshold Voltage

Vr

K = Vo1

K-0.4

K-0.25

K -0.1

V

Reset Threshold Hysteresis

Vrth

Note1

20

50

100

mA