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TEA1733T_1307 Scheda tecnica(PDF) 5 Page - NXP Semiconductors

Il numero della parte TEA1733T_1307
Spiegazioni elettronici  GreenChip SMPS control IC
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

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TEA1733T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 July 2013
5 of 21
NXP Semiconductors
TEA1733T
GreenChip SMPS control IC
7.
Functional description
7.1 General control
The TEA1733T contains a flyback circuit controller, a typical configuration of which is
shown in Figure 3.
7.2 Start-up and UnderVoltage LockOut (UVLO)
Initially, the capacitor on the VCC pin is charged from the high voltage mains via resistor
R3.
If VCC is lower than Vstartup, the IC current consumption is low (typically 10 A). When VCC
reaches Vstartup, the IC first waits for the VINSENSE pin to reach the Vstart(VINSENSE)
voltage and PROTECT pin to reach the Vdet(L)(PROTECT) voltage. When both levels are
reached, the IC charges the ISENSE pin to the Vstart(soft) level and starts switching. In a
typical application, the supply voltage is taken over by the auxiliary winding of the
transformer.
If a protection is triggered the controller stops switching. Depending on the protection
triggered, the protection causes a restart or latches the converter to an off-state.
A restart caused by a protection rapidly charges the OPTIMER pin to 4.5 V (typical). The
TEA1733T enters Power-down mode until the OPTIMER pin discharges down to 1.2 V
(typical). In Power-down mode, the IC consumes a very low supply current (10
Atypical)
and the VCC pin is clamped at 22 V (typical) by an internal clamp circuit. When the
voltage on pin OPTIMER drops below 1.2 V (typical) and the VCC pin voltage is above the
VCC start-up voltage (See Figure 4), the IC restarts.
When a latched protection is triggered, the TEA1733T immediately enters Power-down
mode. The VCC pin is clamped to a voltage just above the latch protection reset voltage
(Vrst(latch) +1V).
Fig 3.
Typical configuration
001aan639
TEA1733T
5
6
7
8
4
3
2
1
R1
R2
R3
R4
Z1
C4
R8
C5
R9
C3
C1
C2
R7
C6
R6
R10
S1
R5
Θ
DRIVER
GND
VCC
ISENSE
VINSENSE
PROTECT
CTRL
OPTIMER


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