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74LVC1G126GN Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74LVC1G126GN Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 21 page 74LVC1G126 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 12 — 2 July 2012 9 of 21 NXP Semiconductors 74LVC1G126 Bus buffer/line driver; 3-state 12. Waveforms Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Input A to output Y propagation delay times mna128 A input Y output tPHL tPLH GND VI VM(1) VM(1) Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. 3-state enable and disable times mna646 tPLZ tPHZ output disabled output enabled VY VX output enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VCC VOL VOH VM GND GND tPZL tPZH VM VM Table 9. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH 0.3 V |
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