Motore di ricerca datesheet componenti elettronici |
|
AD7568BPZ Scheda tecnica(PDF) 4 Page - Analog Devices |
|
AD7568BPZ Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 14 page AD7568 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Parameter Rating VDD to DGND −0.3 V to +6 V IOUT1 to DGND −0.3 V to VDD +0.3 V IOUT2 to DGND −0.3 V to VDD +0.3 V Digital Input Voltage to DGND −0.3 V to VDD +0.3 V VRFB, VREF to DGND ±15 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range Commercial Plastic (B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Power Dissipation (Any Package) to 75°C 250 mW Derates above 75°C by 10 mW/°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 Transient currents of up to 100 mA will not cause SCR latch-up. PIN DESCRIPTION Mnemonic Description VDD Positive Power Supply. This is 5 V ± 5%. DGND Digital Ground. AGND Analog Ground VREFA to VREFH DAC Reference Inputs. RFBA to RFBH DAC Feedback Resistor Pins. IOUTA to IOUTH DAC Current Output Terminals. AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system. CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock line to avoid timing issues. FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low. SDIN Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally comes the three DAC select bits. These determine which DAC in the device is selected for loading. SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration. A0 Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this. LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the input latches. CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero. – 4 – REV. C |
Codice articolo simile - AD7568BPZ |
|
Descrizione simile - AD7568BPZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |