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SI4012-C1001GT Scheda tecnica(PDF) 8 Page - Silicon Laboratories |
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SI4012-C1001GT Scheda tecnica(HTML) 8 Page - Silicon Laboratories |
8 / 50 page Si4012 8 Rev 1.1 2. Typical Application Schematic Notes: 1. The Si4012 has internal 50 k pull-up resistors. Additional optional external pull-up resistors may be added should the board design required it. 2. See note about how to choose the value of C3 in "5.2.10. PROPERTY: XO_CONFIG" on page 39. VDD XTAL TXP GND TXM Si4012 1 2 3 4 5 Optional C3 X1 C2 CR2032 Coin Cell 1.8 to 3.6 V Loop Antenna C1 SCL SDN nIRQ LED SDA 10 9 8 7 6 Host MCU D1 R1 R2 See Note 1 1 µF See Note 2 |
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