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AD5360BCPZ1 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD5360BCPZ1 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 28 page AD5360/AD5361 Rev. A | Page 11 of 28 Pin No. Mnemonic Description LQFP LFCSP 38 40 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage. 43, 51 45, 53 DGND Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane. 44, 50 46, 52 DVCC Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 45 47 SYNC Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See , , and the section for more details. Figure 4 Figure 5 Serial Interface 46 48 SCLK Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 47 49 SDI Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 48 50 PEC Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up that goes low if the packet error check fails. 49 51 SDO Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 52 54 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. EP Connect to VSS Exposed Paddle. |
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