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FM24V01-GTR Scheda tecnica(PDF) 11 Page - Cypress Semiconductor |
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FM24V01-GTR Scheda tecnica(HTML) 11 Page - Cypress Semiconductor |
11 / 15 page FM24V01 - 128Kb I2C FRAM Document Number: 001-84459 Rev. *A Page 11 of 15 AC Parameters (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified) F/S-mode (CL<500pF) HS-mode (CL<100pF) Symbol Parameter Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 1.0 0 3.4 MHz 1 tLOW Clock Low Period 500 160 ns tHIGH Clock High Period 260 60 ns 4 tAA SCL Low to SDA Data Out Valid 450 130 ns tBUF Bus Free Before New Transmission 0.5 0.3 s tHD:STA Start Condition Hold Time 260 160 ns tSU:STA Start Condition Setup for Repeated Start 260 160 ns tHD:DAT Data In Hold 0 0 ns tSU:DAT Data In Setup 50 10 ns 3 tR Input Rise Time 120 80 ns 2 tF Input Fall Time 120 80 ns 2 tSU:STO Stop Condition Setup 260 160 ns tDH Data Output Hold (from SCL @ VIL) 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 5 ns Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations. 1. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max). 2. This parameter is periodically sampled and not 100% tested. 3. In HS-mode and VDD < 2.7V, the tSU:DAT (min.) spec is 15 ns. 4. In HS-mode and VDD < 2.7V, the tHIGH (min.) spec is 100 ns. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (SDA) - 8 pF 1 CIN Input Capacitance - 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V) Symbol Parameter Min Max Units Notes tVR VDD Rise Time 50 - s/V 1,2 tVF VDD Fall Time 100 - s/V 1,2 tPU Power Up (VDD min) to First Access (Start condition) 250 - s 3 tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tREC Recovery Time from Sleep Mode - 400 s Notes 1. This parameter is characterized and not 100% tested. 2. Slope measured at any point on VDD waveform. 3. Applies to VDD > 2.7V. When powering up to VDD < 2.7V, the tPU limit is 500 s. |
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