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FM24CL64B-GA Scheda tecnica(PDF) 7 Page - Cypress Semiconductor

Il numero della parte FM24CL64B-GA
Spiegazioni elettronici  64Kb Serial 3V F-RAM Memory
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24CL64B-GA Scheda tecnica(HTML) 7 Page - Cypress Semiconductor

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FM24CL64B - Automotive Temp.
Document Number: 001-84457 Rev. *A
Page 7 of 13
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24CL64B acknowledges the address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read
command to be issued with the slave address LSB set
to a „1‟. The operation is now a current address read.
S
A
Slave Address
1
Data Byte
1
P
By Master
By F-RAM
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 7. Current Address Read
S
A
Slave Address
1
Data Byte
1 P
By Master
By F-RAM
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Data Byte
A
Acknowledge
Figure 8. Sequential Read
S
A
Slave Address
1
Data Byte
1 P
By Master
By F-RAM
Start
Address
Stop
No
Acknowledge
Data
S
A
Slave Address
0
Address MSB
A
Start
Address
Acknowledge
Address LSB
A
Figure 9. Selective (Random) Read


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