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FM93C66 Rev. C.1

SYNCHRONOUS DATA TIMING

CS

SK

DI

DO (Data Read)

DO (Status Read)

Valid Status

Valid

Input

Valid

Input

Valid

Output

Valid

Output

CS

SK

DI

DO

High - Z

Dummy

Bit

1

1

0

A7

A6

A1

A0

0

D15

D1

D0

;;;;;;;;;;;;;;

;;;;;;;;;;;;;;

;;;

;;;

READ CYCLE (READ)

Address

Bits(8)

Star t

Bit

Opcode

Bits(2)

93C66:

Address bits patter n -> User defined

Timing Diagrams

Address

Bits(8)

CS

SK

DI

DO

High - Z

WRITE ENABLE CYCLE (WEN)

Star t

Bit

93C66:

Address bits patter n -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Opcode

Bits(2)

1

0

0

A7

A6

A1

A0