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FM93C66AE Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor |
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FM93C66AE Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor |
8 / 13 page 8 www.fairchildsemi.com FM93C66A Rev. B.1 tCSS SYNCHRONOUS DATA TIMING CS SK DI DO (Data Read) DO (Status Read) Valid Status tDIS tDIH tPD tDH tSV tSKH tSKL tCSH tDF tDF tPD Valid Input Valid Input Valid Output Valid Output CS SK DI DO High - Z Dummy Bit 1 1 0 A1 A0 0 D1 D0 ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; tCS ;;; ;;; READ CYCLE (READ) Address Bits(8/9) Star t Bit Opcode Bits(2) 93C66A (ORG=1; A n=A7; Dn=D15): Address bits patter n -> A7-A6-A5-A4-A3-A2-A1-A0; User defined 93C66A (ORG=0; A n=A8; Dn=D7): Address bits patter n -> A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined A n A n-1 D n Timing Diagrams Address Bits(8/9) CS SK DI DO High - Z WRITE ENABLE CYCLE (WEN) Start Bit Opcode Bits(2) 1 0 0 A1 A0 tCS A n A n-1 93C66A (ORG=1; A n=A7): Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1) 93C66A (ORG=0; A n=A8): Address bits pattern -> 1-1-x-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1) |
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