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FM93C46AV Scheda tecnica(PDF) 10 Page - Fairchild Semiconductor |
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FM93C46AV Scheda tecnica(HTML) 10 Page - Fairchild Semiconductor |
10 / 13 page 10 www.fairchildsemi.com FM93C46A Rev. C.1 Timing Diagrams (Continued) CS SK DI DO High - Z High - Z CLEARING READY STATUS Star t Bit Note: This Star t bit can also be par t of a next instr uction. Hence the cycle can be continued(instead of getting ter minated, as shown) as if a new instr uction is being issued. Busy Ready Address Bits(6/7) CS SK DI DO High - Z tCS ERASE CYCLE (ERASE) Star t Bit Opcode Bits(2) 1 1 1 A1 A0 Busy Ready tWP A n A n-1 93C46A (ORG=1; A n=A5): Address bits patter n -> A5-A4-A3-A2-A1-A0; User defined 93C46A (ORG=0; A n=A6): Address bits patter n -> A6-A5-A4-A3-A2-A1-A0; User defined Address Bits(6/7) CS SK DI DO High - Z tCS ERASE ALL CYCLE (ERAL) Start Bit Opcode Bits(2) 1 0 0 A1 A0 Busy Ready tWP 93C46A (ORG=1; A n=A5): Address bits pattern -> 1-0-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1) 93C46A (ORG=0; A n=A6): Address bits pattern -> 1-0-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1) A n A n-1 |
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