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FM24C09 Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor |
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FM24C09 Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor |
5 / 14 page 5 www.fairchildsemi.com FM24C08U/09U Rev. A.3 AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC x 0.3 to VCC x 0.7 Output Load 1 TTL Gate and CL = 100 pF Bus Timing ;; SCL SDA IN SDA OUT tF tLOW tHIGH tR tLOW tAA tDH tBUF tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO 0.9VCC 0.1VCC 0.7VCC 0.3VCC Read and Write Cycle Limits (Standard and Low V CC Range 2.7V - 5.5V) Symbol Parameter 100 KHz 400 KHz Units Min Max Min Max fSCL SCL Clock Frequency 100 400 KHz T I Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN 100 50 ns Pulse width) t AA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs t BUF Time the Bus Must Be Free before 4.7 1.3 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs t LOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs t SU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) t HD:DAT Data in Hold Time 0 0 ns tSU:DAT Data in Setup Time 250 100 ns t R SDA and SCL Rise Time 1 0.3 µs t F SDA and SCL Fall Time 300 300 ns t SU:STO Stop Condition Setup Time 4.7 0.6 µs t DH Data Out Hold Time 300 50 ns t WR Write Cycle Time (Note 4) 4.5V to 5.5V V CC 10 10 ms 2.7V to 4.5V VCC 15 15 Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the FM24C08U/09U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer "Write Cycle Timing" diagram. AC Testing Input/Output Waveforms |
Codice articolo simile - FM24C09 |
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Descrizione simile - FM24C09 |
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