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FM24C05UV Scheda tecnica(PDF) 6 Page - Fairchild Semiconductor |
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FM24C05UV Scheda tecnica(HTML) 6 Page - Fairchild Semiconductor |
6 / 14 page 6 www.fairchildsemi.com FM24C04U/05U Rev. A.3 SDA SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Master Transmitter Slave Receiver Master Transmitter/ Receiver VCC VCC SDA SCL 24C02/03 VCC VCC A0 A1 A2 VSS 24C02/03 A0 A1 A2 VSS 24C04/05 A1 A2 VSS 24C08/09 A2 VSS VCC To V SS To V SS To V SS VCC VCC VCC To V CC To V SS To V SS To V CC To V SS To V CC Typical System Configuration Note: Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k Ω) Example of 16K of Memory on 2-Wire Bus Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices. The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state. It is recommended that the total line capacitance be less than 400pF Device Address Pins Present Memory Size # of Page A0 A1 A2 Blocks FM24C02U/03U Yes Yes Yes 2048 Bits 1 FM24C04U/05U No Yes Yes 4096 Bits 2 FM24C08U/09U No No Yes 8192 Bits 4 FM24C16U/17U No No No 16,384 Bits 8 SDA SCL STOP CONDITION START CONDITION WORD n 8th BIT ACK tWR Write Cycle Timing Note: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. |
Codice articolo simile - FM24C05UV |
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Descrizione simile - FM24C05UV |
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