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FM1233BDS3X Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor |
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FM1233BDS3X Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor |
3 / 6 page 3 www.fairchildsemi.com FM1233B Rev. D Pin Descriptions Circuit Timing When operating properly with 5V VCC (for example), RESET will also be about 5V. When VCC starts to fall, RESET will follow it down as shown. When VCC drops below VTH, RESET drops to ground (“issues a RESET”) and stays there unless VCC also falls below its minimum operating voltage, approx. 1V. At this point, the supervisor loses control, and its output may rise, only to again follow VCC down to the ground. When VCC begins to rise, RESET follows it until 1.0V or so is reached, whereupon the device regains control, RESET is pulled to ground, etc. When VCC rises above VTH, RESET comes out of RESET 140 ms later. If it is required that a lower value than GND + 1.0V is needed on RESET signal during VCC ≤ 1V, a 100K resistor may be used on the device output to GND. Pin Number Name Function 1 GND GROUND 2 RESET RESET remains LOW while VCC is below VTH, and for at least 140ms after VCC rises above VTH. 3VCC 3.3V VTH 1V GND 3.3V VTH 1V GND VCC RESET 140ms (min) |
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