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74LVC02ADB Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LVC02ADB Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 14 page 74LVC02A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 16 November 2011 2 of 14 NXP Semiconductors 74LVC02A Quad 2-input NOR gate 4. Functional diagram 5. Pinning information 5.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate mna216 1A 1B 1Y 3 2 1 2A 2B 2Y 6 5 4 3A 3B 3Y 9 8 10 4A 4B 4Y 12 11 13 mna217 1 1 1 1 1 3 2 4 6 5 10 9 8 13 12 11 mna215 A B Y (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 02 1Y VCC 1A 4Y 1B 4B 2Y 4A 2A 3Y 2B 3B GND 3A 001aac919 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac920 02 Transparent top view 2B 3B 2A 3Y 2Y 4A 1B 4B 1A 4Y 6 9 5 10 4 11 3 12 2 13 terminal 1 index area GND(1) |
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