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DAC0830 Scheda tecnica(PDF) 3 Page - Texas Instruments

Il numero della parte DAC0830
Spiegazioni elettronici  DAC0830/DAC0832 8-Bit 關P Compatible, Double-Buffered D to A Converters
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

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DAC0830, DAC0832
www.ti.com
SNAS534B – MAY 1999 – REVISED MARCH 2013
Operating Conditions
Temperature Range
TMIN≤TA≤TMAX
Part numbers with “LCN” suffix
0°C to +70°C
Part numbers with “LCWM” suffix
0°C to +70°C
Part numbers with “LCV” suffix
0°C to +70°C
Part numbers with “LCJ” suffix
−40°C to +85°C
Part numbers with “LJ” suffix
−55°C to +125°C
Voltage at Any Digital Input
VCC to GND
Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX.
(1) For all other limits
TA=25°C.
VCC = 5 VDC ±5%
VCC = 4.75 VDC
VCC = 12 VDC ±5%
VCC = 15.75 VDC
See
Limit
to 15 VDC ±5%
Parameter
Conditions
Note
Units(2)
Tested
Design
Typ(3)
Limit(4)
Limit(5)
CONVERTER CHARACTERISTICS
Resolution
8
8
8
bits
Linearity Error Max
Zero and full scale adjusted
See(6)
−10V≤VREF≤+10V
and (2)
DAC0830LJ & LCJ
0.05
0.05
% FSR
DAC0832LJ & LCJ
0.2
0.2
% FSR
DAC0830LCN, LCWM &
0.05
0.05
% FSR
LCV
DAC0831LCN
0.1
0.1
% FSR
DAC0832LCN, LCWM &
0.2
0.2
% FSR
LCV
Differential Nonlinearity
Zero and full scale adjusted
See(6)
Max
−10V≤VREF≤+10V
and (2)
DAC0830LJ & LCJ
0.1
0.1
% FSR
DAC0832LJ & LCJ
0.4
0.4
% FSR
DAC0830LCN, LCWM &
0.1
0.1
% FSR
LCV
DAC0831LCN
0.2
0.2
% FSR
DAC0832LCN, LCWM &
0.4
0.4
% FSR
LCV
Monotonicity
−10V≤VREF
LJ & LCJ
See(6)
8
8
bits
≤+10V
LCN, LCWM & LCV
8
8
bits
Gain Error Max
Using Internal Rfb
See(7)
±0.2
±1
±1
% FS
−10V≤VREF≤+10V
%
Gain Error Tempco Max
Using internal Rfb
0.0002
0.0006
FS/°C
(1)
Boldface tested limits apply to the LJ and LCJ suffix parts only.
(2)
The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate
dependence on a particular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the
DAC0830 is “0.05% of FSR (MAX)”. This ensures that after performing a zero and full scale adjustment (see sections Zero Adjustment
and Full-Scale Adjustment), the plot of the 256 analog voltage outputs will each be within 0.05%×VREF of a straight line which passes
through zero and full scale.
(3)
Typicals are at 25°C and represent most likely parametric norm.
(4)
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(5)
Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
(6)
For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The
linearity error is degraded by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will
introduce an additional 0.01% linearity error.
(7)
Specified at VREF=±10 VDC and VREF=±1 VDC.
Copyright © 1999–2013, Texas Instruments Incorporated
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