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Si5855DC Scheda tecnica(PDF) 7 Page - Vishay Siliconix |
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Si5855DC Scheda tecnica(HTML) 7 Page - Vishay Siliconix |
7 / 9 page Package Information Vishay Siliconix Document Number: 71151 15-Jan-04 www.vishay.com 1 1206-8 ChipFETR c E E1 e D A 65 7 8 34 2 1 4 L 567 8 432 1 4 S b 2X 0.10/0.13 R Backside View x NOTES: 1. All dimensions are in millimeaters. 2. Mold gate burrs shall not exceed 0.13 mm per side. 3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. Dimensions exclusive of mold gate burrs. 5. No mold flash allowed on the top and bottom lead surface. DETAIL X MILLIMETERS INCHES Dim Min Nom Max Min Nom Max A 1.00 − 1.10 0.039 − 0.043 b 0.25 0.30 0.35 0.010 0.012 0.014 c 0.1 0.15 0.20 0.004 0.006 0.008 c1 0 − 0.038 0 − 0.0015 D 2.95 3.05 3.10 0.116 0.120 0.122 E 1.825 1.90 1.975 0.072 0.075 0.078 E1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.65 BSC 0.0256 BSC L 0.28 − 0.42 0.011 − 0.017 S 0.55 BSC 0.022 BSC 5_Nom 5_Nom ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547 |
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