Motore di ricerca datesheet componenti elettronici |
|
AD7528LN Scheda tecnica(PDF) 3 Page - Analog Devices |
|
AD7528LN Scheda tecnica(HTML) 3 Page - Analog Devices |
3 / 8 page PLCC 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 TOP VIEW (Not to Scale) PIN 1 IDENTIFIER VREF A DGND DAC A/DAC B (MSB) DB7 DB6 VREF B VDD WR CS DB0 (LSB) AD7528 VDD = +5 V VDD = +15 V Parameter Version 1 TA = +25 °CT MIN, TMAX TA= +25 °CT MIN, TMAX Units Test Conditions/Comments CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111. VREF A to OUT B All –77 –77 dB typ VREF A = 20 V p-p Sine Wave @ 100 kHz VREF B = 0 V see Figure 6. VREF B to OUT A –77 –77 dB typ VREF A = 20 V p-p Sine Wave @ 100 kHz VREF A = 0 V see Figure 6. DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTlON All –85 –85 dB typ VIN = 6 V rms @ 1 kHz NOTES 1Temperature Ranges are J, K, L Versions: –40 °C to +85°C A, B, C Versions: –40 °C to +85°C S, T, U Versions: –55 °C to +125°C 2Specifications applies to both DACs in AD7528. 3Guaranteed by design but not production tested. 4Logic inputs are MOS Gates. Typical input current (+25 °C) is less than 1 nA. 5These characteristics are for design guidance only and are not subject to test. 6Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to DGND. Specifications subject to change without notice. AD7528, ideal maximum output is VREF – 1 LSB. Gain error of both DACs is adjustable to zero with external resistance. Output Capacitance Capacitance from OUT A or OUT B to AGND. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VREF A, VREF B = AGND. Propagation Delay This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value. Channel-to-Channel Isolation The proportion of input signal from one DAC’s reference input which appears at the output of the other DAC, expressed as a ratio in dB. Digital Crosstalk The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Speci- fied in nV secs. PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS (TA = +25 °C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VPIN2, VPIN20 to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V Power Dissipation (Any Package) to +75 °C . . . . . . . 450 mW Derates above +75 °C by . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Range Commercial (J, K, L) Grades . . . . . . . . . . . –40 °C to +85°C Industrial (A, B, C) Grades . . . . . . . . . . . . –40 °C to +85°C Extended (S, T, U) Grades . . . . . . . . . . . –55 °C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300 °C CAUTION: 1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on uncon- nected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 2. Do not insert this device into powered sockets. Remove power before insertion or removal. TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB max over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the AD7528 REV. B –3– DIP, SOIC TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD7528 DB4 DB5 DB6 OUT A RFB A VREF A (MSB) DB7 DAC A/DAC B DGND DB3 DB2 DB1 RFB B VREF B VDD DB0 (LSB) CS WR AGND OUT B |
Codice articolo simile - AD7528LN |
|
Descrizione simile - AD7528LN |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |